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Let's think of your CPU as a construction worker (a builder) who's building a house and the cache as his tool bag. To avoid having to keep popping out to his van he loads his tool bag with tools based on what he thinks he's likely to need for the job. If he gets his tool selection wrong he has to stop what he's doing and nip out to the van and get the right one. In cache terms this is called a "miss" because the required data wasn't available when requested and this clearly slows down the progress of the job. If however the tool he needs is right there in his tool bag then this is recorded as a "hit", the data was available when requested and this allows him to continue working almost uninterrupted.
So how do we try to keep our builder busy and stop him having to keep getting tools from the van? Well, there are two ways to achieve this. Firstly, hire an intelligent guy who's more likely to guess correctly when he selects the tools in the first place, or secondly, buy him a bigger tool bag so he can carry more tools with him. The former is known as a hardware data prefetch, a routine which intelligently anticipates data (tools) the processor (builder) will need based on the instruction stream executed (job that needs doing). The second solution is where Barton comes in. AMD have now now doubled the size of our builder's tool bag, or should I say they've doubled the amount of level 2 cache available to the CPU, from a previous 256k to a now rather generous 512k which combined with the 128k of level 1 cache makes a full 640k of on-die, full speed cache and one very efficient builder!! In this scenario we could perhaps think of level1 cache as being our man's tool belt, so the very commonly used tools would be here in the belt. So you see how we have several "layers" of options available to try to make the job more efficient. If the required tool isn't on our builder's belt then he'll have to stoop and check his tool bag, and if it's not here the only option left is to pop out to the van to get it. So it is with cache. If the data isn't in L1 so the CPU checks L2. If it's not there then system memory must be accessed. If you're wondering where the hard drive fits in to our building example then that I'm afraid is a trip to the local builder's merchants!


Dr Escreveu:Nos processadores antigos (Pentium II e predecessores) a cache L1 comunicava com o núcleo do processador ao dobro da frequência com que esta mesma L1 comunicava com a L2. Nos processadores actuais, esta frequência é igual em ambos os sentidos, ou seja, os dados que trafegam entre o núcleo do processador e a cache L1, assim como os dados que trafegam entre a cache L1 e L2, andam à frequência do próprio processador, que no caso de um Pentium M 715 é de 1.6 Ghz.
Cumprimentos.



Gentil Cliente,
Gostaríamos de informar-lhe que o tanto oTravelmate 4000 quanto o 4500 possuem os processador Intel Pentium M processador 715.
A diferença é que o TM 4000 possui1MB L2 Cache, enquanto que o TM4500 possui 2MB L2 Cache. Para maiores informações sobre nossos produtos consultar os nosso aite : www.acer-pt.com.
Atenciosamente
Acer Suporte Comercial

eu diria sem sombra para duvidas que vale a pena optar pelo WLMi... vai ter caracteristicas que mais tarde nao te vais importar nadinha de as ter



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